This invention relates generally to the field of electronic devices, and more particularly relates to electrolytic plating of metals onto printed circuit boards and the like.
Those of ordinary skill in the art will be familiar with numerous applications involving the mounting and interconnecting of electronic components, such as semiconductor devices and the like, onto printed circuit boards. A printed circuit board (PCB) consists essentially of a sheet of insulating substrate, such as phenolic, glass-impregnated epoxy, polyimide, FR4, FR5, or the like, having a predefined pattern of thin conductive paths disposed on one or both sides. The conductive paths, sometimes referred to as xe2x80x9ctraces,xe2x80x9d are typically made of a metal, and define electrical connections between components such as integrated circuits mounted on the PCB.
Existing and emerging technologies are increasingly making use of PCBs. Cases in point include the so-called xe2x80x9cboard-on-chipxe2x80x9d and xe2x80x9cchip-on-boardxe2x80x9d semiconductor device mounting technologies, in which individual semiconductor dies are mounted directly onto (or vice versa) a PCB without prior encapsulation of the dies. Board-on-chip and chip-on-board technologies advantageously allow for greater densities of electronic components to be mounted in a given PCB area as compared with pre-encapsulated device mounting technologies, including surface-rib mount approaches. Higher device densities, in turn, lead to desirable miniaturization of electronic products.
At present, copper is the most prevalent metal used to form conductive metal PCB traces. Various techniques are known for forming copper PCB traces. These include a subtractive process, in which a sheet of copper is laminated to the surface of the PCB substrate and then selectively etched away leaving the desired pattern of traces, and an additive process in which copper is plated onto the PCB substrate in the desired pattern, such that no subsequent etching is required. U.S. Pat. No. 4,581,301 to Michaelson entitled xe2x80x9cAdditive Adhesive Based Process for the Manufacture of Printed Circuit Boardsxe2x80x9d provides a fair overview of various trace-forming techniques for PCB manufacture.
In some applications, it is known to be desirable for selected portions of copper PCB traces to be subsequently plated with another metal, for example a precious metal. Although copper is a very good electrical conductor, its conductivity is inferior to other materials. In applications where minimizing electrical resistance may be particularly critical, introduction of a metals with a conductivity better than that of copper may be beneficial. Furthermore, in some applications it is necessary to perform a so-called wire-bonding operation in which a very fine wire is applied to extend from a bond pad on a semiconductor device to a specific location on a PCB trace, and it is known to those of ordinary skill in the art that copper is a less than ideal metal for establishing a wire bond. Making PCB traces entirely out of a material other than copper, for example, silver or gold, would eliminate this problem, but in most cases would be prohibitively expensive and could give rise to other manufacturing issues. Accordingly, it is sometimes desirable to introduce a metal more conducive to wire bonding at selected discrete sites on PCB traces.
Various methods for selectively applying precious metals onto copper PCB traces are known to those of ordinary skill in the art, with the most prevalent methods involving anodic or cathodic electrolytic plating. To accomplish such selective plating, the surface of the PCB must first be masked to leave exposed only the selected areas to be plated. A sufficiently large positive or negative plating voltage is then applied to the traces and the PCB is immersed in a plating bath containing the precious metal. The precious metal is electrolytically attracted to and bonded to the exposed selected metal trace areas, while the remaining masked areas are left undisturbed. Once the desired areas have been plated, the mask layer may be removed.
One difficulty which can arise with electrolytic plating of precious metals onto PCB traces relates to the application of the plating voltages to the traces during the electrolytic plating process. More often than not, a PCB will have multiple electrically isolated copper traces formed thereon, and the traces are likely to be dispersed across the entire surface of the PCB. In order to spot-plate metals onto more than one separate trace, some means must be provided for applying the necessary electroplating voltage to each trace. Moreover, to facilitate the plating process, the electroplating voltage is preferably applied at a point at or substantially near the periphery of the PCB, whereas some traces to be spot-plated may not extend to the periphery of the PCB.
To address these issues, one approach taken in the prior art is to provide a plating bus bar for each trace (or at least for each trace upon which plating is to occur), with each bus bar extending to a single common plating voltage contact located at or near an edge of the PCB. During the plating process, the plating voltage is applied to the common plating voltage contact, with the plating voltage being conducted to each trace to be plated via a respective plating bus bar. After completion of the plating process, a further etching step is performed to sever or decouple the various plating bus bars at strategic locations so as to electrically disconnect the respective trace from the common plating voltage contact.
There are several potential disadvantages to this approach. First, the need to provide plating bus bars consumes valuable area on the PCB can interfere with the overall layout of the traces. This can have an undesirable adverse impact upon the overall necessary size of PCBs, and, consequently upon the size of the electronic devices into which the PCBs are to be installed.
Another potential drawback of providing plating bus bars to facilitate spot-plating of precious metals relates to the process of decoupling the bus bars from the operational traces once the bus bars have performed their intended function in the plating process. As noted above, one common method of decoupling the bus bars involves an extra etching step in which the bus bar is etched away at some point. Typically, this etching step involves selectively masking the PCB leaving small xe2x80x9cwindowsxe2x80x9d over the bus bars to be severed, and then applying an etchant to remove the metal exposed in those windows.
In addition to undesirably adding an extra masking step and an extra etching step to the PCB fabrication process, the process of decoupling the bus bars presents certain technical challenges. As those of ordinary skill in the art will appreciate, modern PCBs can have a great many traces formed thereon, and these traces may be very small and closely spaced. As a its result, the alignment of the masking layer applied to expose only the windows within which the bus bars are to be severed becomes quite critical. Misalignment of the mask can lead to the severing of traces not intended to be severed and/or to the failure to sever the plating bus bars as intended.
A further potential drawback to the need for providing bus bars for electrolytic plating relates to the electrical characteristics of the traces once the bus bars have been decoupled. Ideally, a bus bar would be severed at a strategic location such that after being severed, the trace that the bus bar served to couple to the plating contact would appear and function electrically as if no bus bar had ever been present. In practical application, on the other hand, this may not always be the case. Often, after a bus bar has been severed, some amount of the bus bar will remain extending from the trace to which it connected; this extending portion is sometimes referred to as a xe2x80x9cplating stub.xe2x80x9d A plating stub may be formed, for example, if the mask window through which the plating bus bar is severed is disposed any distance from the trace itself. This is another example of how alignment of the post-plating mask layer can be critical. Misalignment of this mask prior to the severing etch can undesirably lead to the formation of plating stubs.
It has been observed in the prior art that the presence of plating stubs on PCB traces can adversely affect the electrical performance of the PCB. In modern electronic devices, the electrical signals carried on PCB traces may be very small, and the traces themselves may be very small and closely-spaced. This renders a typical PCB and the components mounted thereon extremely susceptible to capacitive coupling effects and the like. For a given trace pattern on a PCB, the electrical characteristics of the traces may be different depending upon whether plating stubs are present, and even upon the size of the plating stubs, which can be difficult to consistently control as a result of the above-noted mask alignment issues. Moreover, the presence of the portions of the bus bars not etched away during the decoupling process can have adverse capacitive effects upon the operational traces.
In view of the foregoing considerations, the present invention is directed in one respect to a method and apparatus for electrolytic spot-plating of metals onto PCB traces which eliminates the need for plating bus bars, and hence eliminates the formation of plating stubs at the completion of the plating and bus bar severing processes.
In accordance with one aspect of the invention, a PCB substrate is provided that, at least during the plating process, is sufficiently conductive to supply the plating voltage to the various traces formed on the PCB.
In accordance with another embodiment of the invention, a PCB substrate is provided that, subsequent to the plating process can be rendered non-conductive, such that the PCB and the components mounted thereon are permitted to operate properly.